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NJU26040-09D
SRS TruSurround HD/HD4 Decoder
General Description
The NJU26040-09D is a digital audio signal processor that provides the function of TruSurround HD/HD4 + FOCUS and WOW HD. The NJU26040-09D processes all sound sources, such as DVD multi channel signals, CD, AM/FM radio, and TV sound into spacious sound of natural virtual surround by TruSurround HD/HD4 + FOCUS and WOW HD. The applications of NJU26040-09D are suitable for front multi-channel and stereo outputs products such as DVD Receivers, AV Amplifiers, TV, radio-cassettes player, Car Audio or ordinary audio products such as small speakers system.
Package
NJU26040V-09D
FEATURES - Software Front Multi channel outputs by SRS TruSurround HD/HD4 technology WOW HD technology is offered to the stereo I/O product. LFE by SRS TruBass-II technology SRS FOCUS technology (FOCUS is possible to use with TruSurround HD/HD4.) SRS Definition technology improves the perception of clarity and acoustic space Dialog Clarity technology Support mono ~ 5.1ch input, 2.0 ~ 5.1ch output. - Hardware 24bit Fixed-point Digital Signal Processing Maximum System Clock Frequency : 38MHz Max. Digital Audio Interface : 3 Input ports / 3 Output ports Power Supply : 3.3V (Input : 5V tolerant) Package : SSOP32 (Pb-Free) Micro computer interface : I2C bus (standard-mode/100kbps, fast-mode/400kbps), 4-Wire Serial Bus (4-Wire: clock, enable, input data, output data)
The detail hardware specification is described in the "NJU26040 Series Hardware Data Sheet".
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NJU26040-09D
DSP Block Diagram
AD1/SDIN
AD2/SSX
NJU26040-09D
DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R SDO0 SDI0 SDI1 SDI2 C/SW SDO1 BCKI Ls/Rs SDO2 LRI WDC DATA RAM FIRMWARE RAM GPIO MUTEb PROC. SEL
SCL/SCK
SDA/SDOUT
SERIAL HOST INTERFACE
PROGRAM CONTROL
RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT
Fig.1-1 NJU26040-09D Block Diagram
TruSurround HD/HD4 Decoder
SDI0 SDI1 SDI2 mute SDI0 SDI1 SDI2 mute SDI0 SDI1 SDI2 mute Ls/Rs input C/SW input L/R input
Through mode SET TASK mode select Input Trimmer TruSurround Bypass mode TruSurround mode Advanced Bypass mode
Master / Channel Trimmer
L/R
Input Select
C/SW
Input Select
Ls/Rs
Input Select
Fig.1-2 NJU26040-09D Top Level Function Diagram
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NJU26040-09D NJU3555
L out R out C out SW out Ls out Rs out
Master / Channel Trimmer
L/R
Input Trimmer
C/SW Ls/Rs
Through mode Block Diagram
Fig.1-3a NJU26040-09D Function Diagram
Ls
L/R
Input Trimmer
-3dB L C R Rs SW
+
+
+ + + +
TruSurround Bypass Trimmer
Master / Channel Trimmer
+
+
+ +
L out
C/SW Ls/Rs
-3dB
+
+
+
+
R out
-3dB
Lt/Rt input.
-3dB Not Lt/Rt input.
TruSurround Bypass mode Block Diagram Fig.1-3b NJU26040-09D Function Diagram
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NJU26040-09D
L/R C/SW Ls/Rs
C Ls
TruSurround
Dialog Clarity Surround Level
C pre Ls pre Rs pre L pre R pre SW pre
TruSurround Input Trimmer
Mono to Stereo
TruSurround mode Block Diagram (TruSurround mode)
C-ch out disable SW out disable
Input Trimmer
Rs L R SW
C pre
-3dB
Rear out enable C-ch out enable
Definition
HPF + +
Rear out enable
+
Focus
C out Ls out Master / Channel Trimmer
+ HPF
Focus
Ls pre Rs pre
Rear out disable
+
Rear out disable
+
SW out enable
Rs out
HPF
Definition Focus
+ + +
L pre R pre + SW pre +
+ + +
+
SW out enable
Bass Management with TruBass-II(L/R) Bass Management with TruBass-II (SW) Focus Definition
L out R out
+
-6dB
SW out disable
SW out
TruSurround mode Block Diagram (TruSurround mode)
(for WOW HD Front)
TruBass II
Definition
Bass Management with TruBass-II(L/R)
L
Input Trimmer
L R
+ +
FOCUS SRS FOCUS Definition
L out R out SW out
Master / Channel Trimmer
Limiter Headroom Gain
TruSurround Input Trimmer
R SW
+ +
+ +
TruSurround mode Block Diagram (WOW HD mode)
Limiter
+
-6dB
Bass Management with TruBass-II (SW)
WOW HD mode TruBass disable SW out disable TSHD mode TBII select LFE TruBass enable TBII select L/R SW out enable
input(L/R)
HPF
output(L/R)
TruBass II
Front(L/R) Bass Management
LPF TruBass disable
SW out disable
output(SW)
TBII select L/R SW out enable
input(SW)
TruBass enable
TBII select LFE
TruBass II
LFE(SW) Bass Management
Fig.1-3c NJU26040-09D Function Diagram
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NJU26040-09D NJU3555
Dialog Clarity Reffer to TS input mode If C-ch input not exist then C-ch = (L+R)/2. If Ls/Rs input not exist Ls = (L-R)/2, Rs=(R-L)/2 If mono Surround input then Rs = Ls
C output disable
L/R C/SW Ls/Rs
C L R SW Ls Rs
+
C pre
C input enable
TruSurround Input Trimmer
Mono to Stereo
L pre R pre SW pre
Input Trimmer
Rear input enable
Surround Level
Rear output disable
Ls pre Rs pre
C-ch out disable SW out disable
C pre
Definition -3dB
C-ch out enable
HPF + +
Rear out disable
+ Master / Channel Trimmer
FOCUS
C out Ls out
C
Rear out enable
+ HPF
FOCUS
Ls pre Rs pre
Rear out disable
-3dB
+
Rear out enable
+
SW out enable
Rs out
HPF
Definition FOCUS
L pre R pre + SW pre
-3dB
+ + +
+ + +
+
SW out enable
Bass Management with TruBass-II(L/R) Bass Management with TruBass-II (SW) FOCUS Definition
L out R out SW out
-6dB -3dB
+
SW out disable
Advanced Bypass mode Block Diagram
Fig.1-3d NJU26040-09D Function Diagram
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NJU26040-09D
Pin Configuration
VDD
1
32 31 30 29 28
VSS TEST TEST SEL PROC
SDA/SDOUT 2
SCL/SCK 3 AD1/SDIN 4 AD2/SSb 5 RESETb 6 VDD VDD VSS 7 8 9 NJU26040-09D SSOP32
27 MUTEb 26 25 24 23 22 21 20 19 18 17 WDC VDD VSS TEST MCK SDO2 SDO1 SDO0 LRO BCKO
CLKOUT 10 CLK SDI2 SDI1 SDI0 LRI BCKI 11 12 13 14 15 16
Fig.1-4 NJU26040-09D Pin Configuration
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NJU26040-09D NJU3555
Pin Description
Table 1. Pin No. 1, 7, 8, 25 2 3 4 5 6 9, 24, 32 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 30, 31 26 27 28 29
Note : I IO OD I/O+ I/O -
Pin Description Symbol VDD SDA/SDOUT SCL/SCK AD1/SDIN AD2/SSb RESETb VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI BCKO LRO SDO0 SDO1 SDO2 MCK TEST WDC MUTEb PROC SEL I/O OD I I I I O I I I I I I O O O O O O IOD I I I Description Power Supply +3.3V I2C I/O / 4-Wire Serial Output This pin requires a pull-up resistance in both I2C bus and 4-Wire serial mode. 2 I C clock / Serial clock I2C Address / Serial In I2C Address / Serial Enable Reset (RESETb='Low' : DSP Reset) GND OSC Output OSC Clock Input Audio Data Input 2 Audio Data Input 1 Audio Data Input 0 LR Clock Input Bit Clock Input Bit clock Output LR clock Output Audio Data Output 0 (L/R) Audio Data Output 1 (C/SW) Audio Data Output 2 (Ls/Rs) Master Clock Output for A/D, D/A
for Test
(connected to VSS)
Watchdog clock output (open drain output) Master Volume level, After Reset DSP ("1" : 0dB "0" : Mute) After Reset DSP. ( "1" : Normal "0" : Wait from Command ) Select I2C or Serial bus ( `1' : Serial / `0' : I2C-Bus)
: Input : Input (Pull-down) : Output : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional (with Pull-up resistance) : Bi-directional (with Pull-down resistance)
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NJU26040-09D
Digital Audio Interface
The NJU26040-09D audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified. The NJU26040-09D audio interface provides three data input, SDI0, SDI1, SDI2 and three data outputs, SDO0, SDO1, SDO2 as shown in table 2, table 3 and Fig.2. An audio interface input and output data format become the same data format. Table 2. Pin No. 14 13 12 Table 3. Pin No. 19 20 21 Serial Audio Input Pin Symbol Description Audio Data Input 0 SDI0 (L/R, C/SW, Ls/Rs are selected by the command.) Audio Data Input 1 SDI1 (L/R, C/SW, Ls/Rs are selected by the command.) Audio Data Input 2 SDI2 (L/R, C/SW, Ls/Rs are selected by the command.) Serial Audio Output Pin Symbol Description SDO0 SDO1 SDO2 Audio Data Output 0 L / R Audio Data Output 1 C / SW Audio Data Output 2 Ls / Rs
Host Interface
The NJU26040-09D can be controlled via Serial Host Interface (SHI) using either of two serial bus formats: I2C bus or 4-Wire serial bus.(Table 4) Data transfers are in 8 bit packets (1 byte) when using either format. Serial Host Interface Pin Description.(Table 5) Table 4. Pin No. 29 Serial Host Interface Pin Description Symbol Setting Host Interface "Low" I2C bus SEL "High" 4-Wire serial bus
Table 5. Pin No. 2 3 4 5
Serial Host Interface Pin Description Symbol I2C bus Format (I2C bus / Serial) Serial Data Input/Output SDA / SDOUT * (Open Drain Input/Output) SCL / SCK * Serial Clock AD1 / SDIN * I2C bus address Bit1 AD2 / SSb * I2C bus address Bit2
4-Wire Serial bus Format Serial Data Output (Open-Drain Output) Serial Clock Serial Data Input Serial enable
Note : SDA /SDOUT pin is a bi-directional open drain. 2 This pin requires a pull-up resistance in both I C bus and 4-Wire serial mode. * When the power supply (VDD= +3.3V) is supplied to NJU26040, these pins become +5.0V Input tolerant.
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NJU26040-09D NJU3555
I2C bus
When the NJU26040-09D is configured for I2C bus communication during the Reset initialization sequence. I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26040-09A. The AD1 and AD2 pins can arbitrarily set up an address. The I2C address of AD1/AD2 is decided by connection of AD1/AD2 pins. Table 6. I2C bus SLAVE Address
bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 AD2 bit2 0 0 1 1 AD1 bit1 0 1 0 1 R/W bit0 R/W
Start bit
Slave Address ( 7bit )
R/W bit
ACK
* SLAVE address is 0 when AD1/2 is "Low". SLAVE address is 1 when AD1/2 is "High". Note : In case of the NJU26040-09D only single-byte transmission is available. The serial host interface 2 supports "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" I C bus data transfer.
4-Wire Serial Interface
SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = "High". SDOUT is Open-drain output in case of SSb = "Low". SDOUT needs a pull-up resistor when SDOUT is Hi-Z.
SSb SCK SDIN SDOUT Hi-Z bit7
MSB
bit6 bit6 Fig. 4
bit5 bit5
bit1 bit1
bit0
LSB
bit7
bit0
unstabl e
Hi-Z
4-Wire Serial Interface Timing
Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes "High".
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NJU26040-09D
Pin setting
The NJU26040-09D operates default command setting after resetting the NJU26040-09D. In addition, the NJU26040-09D restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDD or VSS through 3.3k resistance. Table 7. Pin No. 28 27 Pin setting Symbol PROC MUTEb Setting "High" "Low" "High" "Low" Function The NJU26040-09D operates default setting after reset. The NJU26040-09D does not operate after reset. Sending start command is required for starting operation. Master volume is set 0dB after reset. Master volume is set mute after reset.
WatchDog Clock
The NJU26040-09D outputs clock pulse through WDC (No.26) pin during normal operation. (Table 8) Table 8. WatchDog Clock Output Cycle WDC Output Cycle (Low/High) Time 85ms The NJU26040-09D generates a clock pulse through the WDC terminal after resetting the NJU26040-09D. The WDC clock is useful to check the status of the NJU26040-09D operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26040-09D. When the WDC clock pulse is lost or not normal clock cycle, the NJU26040-09D does not operate correctly. Then reset the NJU26040-09D and set up the NJU26040-09D again.
Note : If input and output of an audio signal stop and an audio interface stops, WDC can't output. That is because it has controlled based on the signal of an audio interface.
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NJU26040-09D Command Table
Table 9. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NJU26040-09D Command Command SET_TASK_CMD AUDIO_FORMAT_CMD SYSTEM_STATE_CMD SAMPRATE_CMD INPUT_SELECT_CMD TSHD_INPUT_MODE_CMD TSHD_OUTPUT_MODE_CMD DF_SELECT_CMD TB2_SETUP_CMD SW_CROSSOVER_FREQ_CMD SRS3D_SETUP_CMD INPUT_TRIM_CMD MASTER_TRIM_CMD LEFT_TRIM_CMD RIGHT_TRIM_CMD CENTER_TRIM_CMD SUBWOOFER_TRIM_CMD
LEFT_SRND_TRIM_CMD Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (SRS Labs. Inc.) is required.
No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Command RIGHT_SRND_TRIM_CMD TSHD_INPUT_TRIM_CMD TSHD_BYPASS_TRIM_CMD TSHD_SRND_LEVEL_CMD DC_CNTRL_CMD FC_FRONT_CNTRL_CMD FC_REAR_CNTRL_CMD TB2_FRONT_CNTRL_CMD TB2_LFE_CNTRL_CMD DF_FRONT_CNTRL_CMD DF_CENTER_CNTRL_CMD SRS3D_SPACE_CNTRL_CMD SRS3D_CENTER_CNTRL_CMD LIMITER_CMD SOFT_RESET_CMD WDC_TEST_CMD START_CMD
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NJU26040-09D
NJU26040-09D Package Dimensions ( SSOP32, Pb-Free )
11.0
+0.3 -0.1
0 ~ 10 17
32
5.6 0.2
7.6 0.3
1 0.75 MAX.
0.65
16 0.15 +0.10 -0.05
0.1 0.22 0.1
+0.10 -0.05
1.15 0.1
0.1
M
0.1
Unit : mm
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0.5 0.2
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NJU26040-09D NJU3555
License Information
The "TruSurround HD", "TruSurround HD4", "WOW HD", "Dialog Clarity", "FOCUS" and "TruBass" technology rights incorporated in the NJU26040-09D are owned by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd.. Purchaser of NJU26040-09D must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the NJU26040-09D must be sent to SRS Labs for review. "TruSurround HD", "TruSurround HD4", "WOW HD", "Dialog Clarity", "FOCUS" and "TruBass" is protected under US and foreign patents issued and/or pending. "TruSurround HD", "TruSurround HD4", "WOW HD", "Dialog Clarity", "FOCUS", "TruBass", SRS and symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the NJU26040-09D, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. For further information, please contact:: SRS Labs, Inc. 2909 Daimler Street. Santa Ana, CA 92705 USA Tel: 949-442-1070 Fax: 949-852-1099 http://www.srslabs.com
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2009-02-10
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